1. Field of the invention
This invention relates to a liquid crystal display device which executes display by applying a drive signal to picture element electrodes for display by means of switching elements. More particularly, it relates to an active-matrix display device with added capacitance used in the said liquid crystal display device and a method for the production of the display device.
2. Description of the prior art
A display pattern is formed on the screen of liquid crystal display devices, EL display devices, plasma display devices, etc., by selectively driving picture element electrodes arranged in a matrix. A voltage is applied between the selected picture element electrode and the opposing electrode positioned opposite the selected picture element electrode so as to optically modulate a display medium disposed therebetween. This optical modulation is observed as the display pattern. One drive method used to drive picture element electrodes is the active-matrix drive method wherein the independent picture element electrodes are arranged in rows and driven by switching elements that are connected with the corresponding picture element electrodes. The switching elements which selectively drive the picture element electrodes are generally thin-film transistor (TFT) elements, metal-insulator-metal (MIM) elements, MOS transistors, diodes, or varistors. Active-matrix drive systems make high-contrast displays possible and are used in liquid crystal television, word processors and computer terminal display devices.
FIG. 9A is a perspective view of an active-matrix liquid crystal display device which employs a conventional active-matrix substrate. FIG. 9B is a cross sectional view of the device of FIG. 9A taken along the line B--B. FIG. 9C is a diagram of the active-matrix substrate used in the device of FIG. 9A. The active-matrix liquid crystal display device has a liquid crystal layer 68 that is sandwiched between the active-matrix substrate 51 on which thin-film transistors (TFT) functioning as switching elements are formed and the opposing substrate 52 positioned opposite the substrate 51. The liquid crystal layer 68 is sealed by a sealant resin 70. This active-matrix substrate 51 has an insulation substrate 50, numerous parallel gate electrode wires 61 disposed on the insulation substrate 50, and numerous source electrode wires 62 which run perpendicular to the wires 61. The gate electrode wires 61 are connected to the corresponding gate electrode terminals 53 running along one edge of the substrate 50. In a similar manner, the source electrode wires 62 are connected to the corresponding source electrode terminals 54 running along another edge of the substrate 50.
As shown in FIG. 9B, the opposing electrodes 65 on the opposing substrate 56 are connected electrically via the connecting electrodes 67 to the opposing electrode terminals 55 on the substrate 50. The orientation films 69 and 69 are formed on the top of the picture element electrodes 64 on the substrate 50 and on top of the opposing electrodes 65 on the opposing substrate 56.
As shown in FIG. 9C, each of the TFTs 63 is positioned near the intersection between the gate electrode wire 61 and the source electrode wire 62. A scanning signal is supplied from the gate electrode wire 61 to the gate electrode of the TFT 63, and a video signal is supplied from the source electrode wire 62 to the source electrode of the TFT 63. The drain electrode of the TFT 63 is connected to the corresponding picture element electrode 64.
This kind of liquid crystal display device performs the display operation as described below. First, a gate ON voltage is applied to the gate electrode wires 61, and all of the TFTs 63 connected to the gate electrode wires 61 become ON. At the same time, a voltage corresponding to the video signal in synchronism with the gate ON signal is applied to the picture element electrodes 64 via the source electrode wires 62. Next, a gate OFF voltage is applied to the above-mentioned gate electrode wires 61, and all of the TFTs 63 connected to these electrode wires 61 become OFF. When the TFTs 63 become OFF, the charge stored in the picture element electrodes 64 is retained. The period of time for which the charge is stored is dependent on the time constant determined by the electrical capacitance of the liquid crystal cell composed of the picture element electrodes 64, the opposing electrodes 65, the liquid crystal layer 68, etc., and the OFF resistance of the TFTs 63. This display operation is repeatedly performed on the gate electrode wires 61 to display the video image on the display device.
However, it is known that the charge retained by the picture element electrodes 64 drops due to the action of the TFTs 63. This drop in voltage is explained using FIG. 10 showing a portion of the TFT 63. FIG. 11 is an equivalent circuit of the TFT 63 of FIG. 10. An amorphous silicon intrinsic semiconductor layer (hereinafter, referred to as a-Si(i) layer) 9 which functions as an electron transit layer is formed as part of the gate electrode wires 61 on the gate electrodes 71 in a manner to sandwich an insulation film therebetween, and then on top of the semiconductor layer 9, the source electrodes 72 connected to the source electrode wires 62 and the drain electrodes 73 connected to the picture element electrodes 64 are formed. A liquid crystal cell 76 is formed between the picture element electrodes 64 and the opposing electrodes 65 (not shown).
The above-mentioned voltage drop is due to the parasitic capacitance Cgd which forms in the area of the part S1 where the drain electrodes 73 and the gate electrodes 71 overlap each other. As shown in FIG. 11, the parasitic capacitance Cgd is formed parallel to the TFT 63. The drop V.sub.shift in the potential of the drain electrodes 73 due to the parasitic capacitance Cgd is given by the following equation. ##EQU1##
wherein Clc is the electrical capacitance due to the liquid crystal cell 76 and the V.sub.gate is the potential difference between the ON signal and the OFF signal applied to the gate electrodes 71.
Due to the presence of this parasitic capacitance Cgd in the TFT 63, when the signal applied to the gate electrodes 71 changes from an ON signal to an OFF signal, the potential difference between the ON signal and the OFF signal is divided by the ratio of the parasitic capacitance Cgd to the capacitance Clc of the liquid crystal cell. Therefore, the potential of the drain electrodes 73 i.e., the potential of the picture element electrodes 64, drops by the amount indicated by V.sub.shift in the above equation.
In order to make the V.sub.shift value small, electrodes 9 1 for added capacitance made from a transparent conductive film are often disposed below the picture element electrodes 64 as shown in FIG. 12. FIGS. 13 and 14 are cross sectional views taken along the lines P--P and Q--Q of FIG. 12. As shown in FIG. 12, the added capacitance electrode wires 91 are parallel to the gate electrode wires 61, and the added capacitance electrode wires 91 positioned below the picture element electrodes 64 are wider than connecting portions for connecting one added capacitance electrode wire to the adjacent added capacitance electrode wire. As shown in FIGS. 13 and 14, the added capacitance electrode wires 91 are formed below a gate insulation film 101 that has been formed under the picture element electrodes 64. The added capacitance C.sub.S forms between parts of the added capacitance electrode wires 91 and the picture element electrodes 64. FIG. 15 is an equivalent circuit on the substrate in FIG. 12. As shown in FIG. 15, since the added capacitance C.sub.S is disposed parallel to the liquid crystal cell capacitance Clc, the above-mentioned voltage drop V.sub.shift is given by the following equation. ##EQU2##
By including an added capacitance C.sub.S in this manner, the voltage drop V.sub.shift can be made small.
However, the added capacitance electrode wires 91 are made from ITO, SnO.sub.2, and other types of transparent conductive films, so they have a larger resistance than do the metal films used for the gate electrode wires 61, etc. When the electrical resistance of the added capacitance electrode wires 91 is large, the time constant of the added capacitance C.sub.S becomes large, which prevents the storage of a sufficiently large charge while the ON signal is being applied to the gate electrodes 71 of the TFT 63. This tendency becomes more pronounced when the display device is made larger because the total length of the added capacitance electrode wires 91 becomes longer. Moreover, as the resolution of the display screen is increased, the number of gate electrode wires 61 increases, so it becomes necessary to shorten the length of time the ON signal is applied to the gate electrodes 71.